-- Engineer: Jeroen Langelaan & Maikel van der Raaij
-- Date: 15-2-2012
-- Version: 1.0

-- Dit gaat over de VGA timing.
-- x_teller en y_teller worden ook gebruikt in het calcul gedeelte.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity VGA_timing is
port(	clock2: in std_logic; -- De 50 MHz klok
		hsync, vsync : out std_logic; 
		video_on : out std_logic; -- Video_on voor naar de latch
		x_tellerout, y_tellerout : out integer range 0 to 1023);
end VGA_timing;

architecture Behavorial of VGA_timing is

	signal x_teller : integer range 0 to 1023;
	signal y_teller : integer range 0 to 1023;
begin	
	process(clock2) 	-- Timing voor VGA wordt in dit proces gedaan.
	begin					-- De timing is voor een resolutie van 640x480.
	if rising_edge(clock2) then
		
			if x_teller = 799 then x_teller <= 0;
				else x_teller <= x_teller + 1; 
			end if;
			if x_teller = 699 then 
				if y_teller = 524 then y_teller <= 0;
					else y_teller <= y_teller + 1;
				end if;
			end if;			
			if ((x_teller > 655) and (x_teller < 752)) then hsync <= '0';
				else hsync <= '1'; 
			end if;
			if ((y_teller = 490) or (y_teller = 491)) then vsync <= '0';
				else vsync <= '1'; 
			end if;
			if ((x_teller < 640) and (y_teller < 480)) then video_on <= '1';
				else video_on <= '0'; 
			end if;
			
	end if;
	end process;
	
	x_tellerout <= x_teller;
	y_tellerout <= y_teller;
	
end behavorial;

-- Deel wat de klok deelt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity klokdeler is
	PORT(	clock : in std_logic;
			clock2 : out std_logic);
end klokdeler;

architecture rtl of klokdeler is
	signal clockdeler : std_logic := '0';
begin
	process(clock)
	begin
		-- Klok wordt elke puls geswitched, dus delen door 2
		if rising_edge(clock) then clockdeler <= not(clockdeler); 
		end if;
	end process;
	clock2 <= clockdeler;
end rtl;

-- Latch aan de uitgang
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity latch is
port(	rgb_uitgang : out std_logic_vector(2 downto 0);
		rgb_ingang : in std_logic_vector(2 downto 0);
		rgb_background : in std_logic_vector (2 downto 0);
		sprite_on : in std_logic;
		clock2 : in std_logic;
		video_on : in std_logic);
end latch;
		
architecture rtl of latch is
begin
	process(clock2)
	begin
		if rising_edge(clock2) then
			-- Als video_on 0 is moet er niks aan de uitgang staan.
			if video_on = '1' then
					if sprite_on = '1' then RGB_uitgang <= rgb_ingang;
						else RGB_uitgang <= rgb_background;
					end if;
				else RGB_uitgang <= "000"; 
			end if;
		end if;
	end process;
end rtl;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package vgapack is

component VGA_timing is
port(	clock2: in std_logic;
		hsync, vsync : out std_logic; 
		video_on : out std_logic; 
		x_tellerout, y_tellerout : out integer range 0 to 1023);
end component;

component klokdeler is
	PORT(	clock : in std_logic;
			clock2 : out std_logic);
end component;

component latch is
port(	rgb_uitgang : out std_logic_vector(2 downto 0);
		rgb_ingang : in std_logic_vector(2 downto 0);
		rgb_background : in std_logic_vector(2 downto 0);
		sprite_on : in std_logic;
		clock2 : in std_logic;
		video_on : in std_logic);
end component;

end vgapack;